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    1  --------------------------------------------------------------------------------
    2  --
    3  -- This VHDL file was generated by EASE/HDL 9.3 Revision 1 from HDL Works B.V.
    4  --
    5  -- Ease library  : uart
    6  -- HDL library   : uart
    7  -- Host name     : Dallas
    8  -- User name     : demo
    9  -- Time stamp    : Fri Jan  7 14:25:57 2022
   10  --
   11  -- Designed by   : EASE example
   12  -- Company       : HDL Works B.V.
   13  -- Project info  : 
   14  --
   15  --------------------------------------------------------------------------------
   16  
   17  --------------------------------------------------------------------------------
   18  -- Object        : Entity uart.uart
   19  -- Last modified : Fri Jan  7 14:21:27 2022
   20  --------------------------------------------------------------------------------
   21  
   22  library ieee;
   23  use ieee.std_logic_1164.all;
   24  use ieee.std_logic_unsigned.all;
   25  use ieee.std_logic_arith.all;
   26  
   27  entity uart is
   28    generic(
   29      dwidth : natural := 8); -- Data width parallel data
   30    port (
   31      addr       : in     std_logic_vector(1 downto 0);
   32      csn        : in     std_logic;
   33      data       : inout  std_logic_vector(dwidth-1 downto 0);
   34      frame_err  : out    std_logic;
   35      parity_err : out    std_logic;
   36      rd         : in     std_logic;
   37      resetn     : in     std_logic;
   38      rx         : in     std_logic;
   39      rxrdy      : out    std_logic;
   40      sclk       : in     std_logic;
   41      tx         : out    std_logic;
   42      txrdy      : out    std_logic;
   43      wr         : in     std_logic);
   44  end entity uart;
   45  
   46  --------------------------------------------------------------------------------
   47  -- Object        : Architecture uart.uart.structure
   48  -- Last modified : Fri Jan  7 14:21:27 2022
   49  --------------------------------------------------------------------------------
   50  
   51  library receiver;
   52  use receiver.receiver;
   53  
   54  architecture structure of uart is
   55  
   56    signal parity_en : std_logic;
   57    signal d_out     : std_logic_vector(dwidth-1 downto 0);
   58    signal d_in      : std_logic_vector(dwidth-1 downto 0);
   59    signal nr_dbits  : std_logic_vector(1 downto 0);
   60    signal stop_2bit : std_logic;
   61  
   62    component transmitter
   63      generic(
   64        dwidth : natural := 8); -- Data width parallel data
   65      port (
   66        addr      : in     std_logic_vector(1 downto 0);
   67        csn       : in     std_logic;
   68        data      : in     std_logic_vector(dwidth-1 downto 0);
   69        nr_dbits  : in     std_logic_vector(1 downto 0);
   70        parity_en : in     std_logic;
   71        resetn    : in     std_logic;
   72        sclk      : in     std_logic;
   73        stop_2bit : in     std_logic;
   74        tx        : out    std_logic;
   75        txrdy     : out    std_logic;
   76        wr        : in     std_logic);
   77    end component transmitter;
   78  
   79    component receiver
   80      generic(
   81        dwidth : natural := 8); -- Data width parallel data
   82      port (
   83        data       : out    std_logic_vector(dwidth-1 downto 0);
   84        frame_err  : out    std_logic;
   85        nr_dbits   : in     std_logic_vector(1 downto 0);
   86        parity_en  : in     std_logic;
   87        parity_err : out    std_logic;
   88        resetn     : in     std_logic;
   89        rx         : in     std_logic;
   90        rxrdy      : out    std_logic;
   91        sclk       : in     std_logic;
   92        stop_2bit  : in     std_logic);
   93    end component receiver;
   94  
   95    component cntrl
   96      generic(
   97        dwidth : natural := 8); -- Data width parallel data
   98      port (
   99        addr      : in     std_logic_vector(1 downto 0);
  100        csn       : in     std_logic;
  101        data      : in     std_logic_vector(dwidth-1 downto 0);
  102        nr_dbits  : out    std_logic_vector(1 downto 0);
  103        parity_en : out    std_logic;
  104        resetn    : in     std_logic;
  105        sclk      : in     std_logic;
  106        stop_2bit : out    std_logic;
  107        wr        : in     std_logic);
  108    end component cntrl;
  109  
  110  begin
  111  
  112    u0: transmitter
  113      generic map(
  114        dwidth => dwidth)
  115      port map(
  116        addr      => addr,
  117        csn       => csn,
  118        data      => d_in,
  119        nr_dbits  => nr_dbits,
  120        parity_en => parity_en,
  121        resetn    => resetn,
  122        sclk      => sclk,
  123        stop_2bit => stop_2bit,
  124        tx        => tx,
  125        txrdy     => txrdy,
  126        wr        => wr);
  127  
  128    u1: receiver
  129      generic map(
  130        dwidth => dwidth)
  131      port map(
  132        data       => d_out,
  133        frame_err  => frame_err,
  134        nr_dbits   => nr_dbits,
  135        parity_en  => parity_en,
  136        parity_err => parity_err,
  137        resetn     => resetn,
  138        rx         => rx,
  139        rxrdy      => rxrdy,
  140        sclk       => sclk,
  141        stop_2bit  => stop_2bit);
  142  
  143    u2: cntrl
  144      generic map(
  145        dwidth => dwidth)
  146      port map(
  147        addr      => addr,
  148        csn       => csn,
  149        data      => d_in,
  150        nr_dbits  => nr_dbits,
  151        parity_en => parity_en,
  152        resetn    => resetn,
  153        sclk      => sclk,
  154        stop_2bit => stop_2bit,
  155        wr        => wr);
  156  
  157  
  158  
  159    data <= d_out when rd = '1' else (others => 'Z');
  160    d_in <= data;
  161  end architecture structure ; -- of uart
  162  
  163  

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