Generated VHDL for the state machine

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   42  
   43  --------------------------------------------------------------------------------
   44  -- Object        : Architecture uart.transmit.fsm
   45  -- Last modified : Mon Jan 10 16:41:36 2022
   46  --------------------------------------------------------------------------------
   47  
   48  architecture fsm of transmit is
   49  
   50    -- State Machine Options:
   51    --  Clock : sclk (Rising edge).
   52    --  State assignment : Enumerate.
   53    --  State decoding : Case construct.
   54    --  Actions on transitions : Clocked.
   55    --  Actions on states : Clocked.
   56  
   57    type state_type is (idle, load, send_data, send_parity, send_stop, stop_mult, 
   58              wait_stop) ;
   59    signal state : state_type;  -- Current State
   60    signal data   : std_logic_vector(dwidth-1 downto 0);
   61    signal cnt    : std_logic_vector(2 downto 0);
   62    signal parity : std_logic;
   63  
   64  
   65  begin
   66    --An other way to add comment
   67  
   68    --FSM comment
   69    state_decoding: process (sclk, resetn) is
   70    begin
   71      if (resetn = '0') then
   72        state <= idle ;
   73        -- def:
   74        tx    <= '1';
   75        txrdy <= '0';
   76        data  <= (others => '0');
   77        cnt   <= (others => '0');
   78        parity<= '0';
   79      elsif (sclk'event and (sclk = '1')) then
   80        lbl_state : case state is
   81          when idle =>
   82            if (ld = '1') then
   83              state <= load ;
   84              -- tx_ld:
   85              data   <= d;
   86              cnt    <= ('0'&nr_dbits) + 4;
   87              parity <= '0';
   88            end if ;
   89          when load =>
   90            if (neg_txclk = '1') then
   91              state <= send_data ;
   92              -- tx_start:
   93              tx <= '0';
   94            end if ;
   95          when send_data =>
   96            if (
   97              neg_txclk = '1' and
   98              cnt /= 0
   99              ) then
  100              state <= send_data ;
  101              -- tx_data:
  102              tx     <= data(0);
  103              parity <= parity XOR data(0);
  104              data   <= '0' & data(7 downto 1);
  105              cnt    <= cnt - 1;
  106  
  107            elsif (
  108              neg_txclk = '1' and
  109              parity_en = '1'
  110              ) then
  111              state <= send_parity ;
  112              -- tx_data:
  113              tx     <= data(0);
  114              parity <= parity XOR data(0);
  115              data   <= '0' & data(7 downto 1);
  116              cnt    <= cnt - 1;
  117  
  118            elsif (neg_txclk = '1') then
  119              state <= send_stop ;
  120              -- tx_data:
  121              tx     <= data(0);
  122              parity <= parity XOR data(0);
  123              data   <= '0' & data(7 downto 1);
  124              cnt    <= cnt - 1;
  125  
  126            end if ;
  127          when send_parity =>
  128            if (neg_txclk = '1') then
  129              state <= send_stop ;
  130              tx <= parity;
  131            end if ;
  132          when send_stop =>
  133            if (
  134              neg_txclk = '1' and
  135              stop_2bit = '1'
  136              ) then
  137              state <= stop_mult ;
  138              -- tx_stop:
  139              tx <= '1';
  140              txrdy <= '1';
  141            elsif (neg_txclk = '1') then
  142              state <= wait_stop ;
  143              -- tx_stop:
  144              tx <= '1';
  145              txrdy <= '1';
  146            end if ;
  147          when stop_mult =>
  148            if (neg_txclk = '1') then
  149              state <= wait_stop ;
  150              -- tx_stop:
  151              tx <= '1';
  152              txrdy <= '1';
  153            end if ;
  154          when wait_stop =>
  155            if (neg_txclk = '1') then
  156              state <= idle ;
  157              -- def:
  158              tx    <= '1';
  159              txrdy <= '0';
  160              data  <= (others => '0');
  161              cnt   <= (others => '0');
  162              parity<= '0';
  163            end if ;
  164        end case lbl_state ;
  165      end if ; --  Reset & Clock
  166    end process state_decoding ;
  167  
  168  end architecture fsm ; -- of transmit
  169  
  170  

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