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| SPR | Title | Released | Description |
|---|---|---|---|
| 2337 | Cadence Allegro Skill interface issues | 5.0.4 | Netlist extraction failed on schematic pages. |
| 2280 | ODB++ reader issues | 5.0.3 | ODB++ reader fails on UNITS statement The reader now uses the 'eda/data' file as netlist, instead of the 'cadnet/netlist' file. |
| Pin group changes Xilinx | 5.0.3 | Moved Xilinx VCCADC... pins to the functional group VCCRIO for 7-series families | |
| Allegro wiring | 5.0.3 | Added Allegro V22.1 to the executable determination. Added warning about missing settings.il SKILL file. |
|
| FPGA Device updates | 5.0.3 |
|
|
| 2264 | Microsemi constraints format changed for PolarFire family | 5.0.2 | The set_io command has changed and is not recognized. |
| 2257 | Unconnected net pattern in the User preferences not stored | 5.0.2 | Any value set for Unconnected net pattern in the User preferences is lost when re-opening the dialog. |
| 2235 | ODB++ components.z file not processed | 5.0.2 | IO Checker only uncompresses the .Z files as they are compressed by Unix compress. .z files with gzip compression (not supported in the standard) are not supported. |
| 2233 | Microsemi pin report by name parser broken | 5.0.2 | Parser reports the functional name (Function column) as the signal name for each pin, instead of the name from the Port column. |
| 2231 | Zuken NDF parser ignores unconnected pins | 5.0.2 | The Zuken NFD parser ignore all lines which don't specify a netname, part_name or pin_label. |
| FPGA Device updates | 5.0.2 |
|
|
| 2202 | Option to save data source locations relative | 5.0.1 | When creating a new project the selected data files are always using a full path. Only after saving the project you can change this to a relative path. |
| 2201 | Support for Lattice Radiant devices | 5.0.1 | Families Certus-NX, CertusPro-NX and MACHXO5-NX have been added. |
| 2192 | Microsemi Igloo2/SmartFusion2 VCCC clock capable pins not in the CLK group | 5.0.1 | As title |
| 2191 | Extract voltage information from other Microsemi Libero report files. | 5.0.1 | Additional data files for voltage extraction could be: <project_name>_bankrpt.rpt <project_name>_compile_netlist_resources.rpt |
| 2189 | Show pin differences for alternate device in the pin view | 5.0.1 | Add filter in both Pin view and Device view to only show pins which differ on the alternate device. |
| 2188 | Rule matching option to allow both normal name and derived name | 5.0.1 | Add option in the matching dialog for each rule. |
| 2187 | Disable annoying beeps | 5.0.1 | User option to disable annoying beep when errors are sent to the console window |
| 2160 | Have a way to easily modify constraint signals names | 5.0.1 | A new dialog is added to change groups of signals using regular expressions. |
| 2147 | Extend Cadence Allegro wiring dialog with a port type. | 5.0.1 | The Allegro CSV wiring can now extract a port type from the CSV file. |
| 2142 | Improve ODB++ support | 5.0.1 | Support for compressed components.Z file in ODB++ directory structure. |
| FPGA Device updates | 5.0.1 |
|
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